CMOS image sensor apparatus with on-chip real-time pipelined JPEG compression module

ABSTRACT

A CMOS imager in which a CMOS image sensor, a color image processing module and an image compression module are all provided on a single die. Both the color image processing module and the image compression module incorporate pipelined architectures to process the image data at a video rate in a massively parallel fashion.

FIELD OF THE INVENTION

The invention relates generally to improved semiconductor imagingdevices and, more specifically, to a CMOS imager provided with anon-chip data compression module.

BACKGROUND OF THE INVENTION

A number of different types of semiconductor-based imagers exist,including charge coupled devices (CCDs), CMOS arrays, photodiode arrays,charge injection devices and hybrid focal plane arrays. Recently,however, CMOS imagers have gained popularity in use in a wide variety ofelectronic devices, because CMOS imagers offer a number of advantagesover other types of imagers. CMOS imagers, for example, are compatiblewith integrated on-chip electronics (control logic and timing, imageprocessing, and signal conditioning such as A/D conversion). CMOSimagers allow random access to the image data. CMOS imagers have lowerfabrication costs as compared with the conventional CCD imagers, sincestandard CMOS processing techniques can be used. Additionally, CMOSimagers have low power consumption because only one row of pixels at atime needs to be active during the readout and there is no chargetransfer (and associated switching) from pixel to pixel during imageacquisition. On-chip integration of electronics is particularlyadvantageous because of the potential to perform many signalconditioning functions in the digital domain (versus analog signalprocessing) as well as to achieve a reduction in system size and cost.

CMOS imagers as discussed above are generally known as discussed, forexample, in Nixon et al., “256×256 CMOS Active Pixel SensorCamera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp.2046-2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEETransactions on Electron Devices, Vol. 41(3) pp. 452-453, 1994 as wellas U.S. Pat. No. 5,708,263, U.S. Pat. No. 5,471,515, and U.S. Pat. No.6,204,524, which are herein incorporated by reference.

Recent advances in CMOS image sensor technology include the integrationof the imager and sophisticated image processing modules on a singledie, as mentioned above. These systems-on-a-chip (SOCs) usually havecost, power consumption and form-factor advantages over the multi-chipsolutions with the same functionality. Furthermore, image processingmodules integrated with CMOS imagers can be fine tuned to the specificproperties of the given imager and to the needs of the targetedapplications. One segment of the market where the low power of CMOSimagers is most advantageous is the mobile devices market. Manycell-phone designs are incorporating image sensors in theirarchitectures. However, bandwidth limitations imposed by wirelesstransmission, together with the desire to employ image sensors withlarge pixel counts, necessitates the use of image compression in thesystem. Many of the existing designs draw on the ability of the on-boardCPU to perform image compression, but at speeds far below video rates.Other available solutions rely on an additional image processing chip toperform color processing and compression.

All of the known solutions require a frame buffer memory to allow forrate conversion between video rate of incoming uncompressed data and therate at which compression can be performed by either system or dedicatedCPU. This leads to increased cost of the imager module and reduced videothroughput of the system. Accordingly, it would be desirable to providea CMOS imager with on-board image compression circuitry which processesimage data in real time, and thus eliminates the need for a frame buffermemory.

SUMMARY OF THE INVENTION

The present invention provides a CMOS imager in which a CMOS imagesensor, a color image processing module and an image compression moduleare all provided on a single die. Both the color image processing moduleand the image compression module incorporate pipelined architectures toprocess the image data at a video rate in a massively parallel fashion.

Additional advantages and features of the present invention will beapparent from the following detailed description and drawings, whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a typical CMOS pixel sensor chip.

FIG. 2 is a block diagram of a preferred embodiment of the presentinvention.

FIG. 3 is a block diagram of the baseline JPEG compression module of thepresent invention.

FIG. 4 is a block diagram of the SRAM Addressing Scheme of the presentinvention.

FIG. 5 is a block diagram of the FIFO & Register Control module of thepresent invention.

FIG. 6 is an illustration of a computer system having a CMOS imageraccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which are shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

FIG. 1 illustrates a block diagram for a typical CMOS imager 10 having apixel array 100 with each pixel cell being constructed in the mannerdisclosed, for example, in U.S. Pat. No. 6,204,524, the disclosure ofwhich is herein incorporated by reference. Pixel array 100 comprises aplurality of pixels arranged in a predetermined number of columns androws. The pixels of each row in array 100 are all turned on at the sametime by a row select line, and the pixels of each column are selectivelyoutput by a column select line. A plurality of rows and column lines areprovided for the entire array 100. The row lines are selectivelyactivated by the row driver 110 in response to row address decoder 120and the column select lines are selectively activated by the columndriver 160 in response to column address decoder 170. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 150 which controls address decoders 120, 170 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 110, 160 which apply driving voltage tothe drive transistors of the selected row and column lines.

In the operation of the FIG. 1 CMOS imager, one of the rows of pixels isselected for readout by using row driver 110 as described above. Allpixels on a selected row are processed simultaneously and sampled onto acapacitor at the bottom of their respective columns. The column-parallelsampling process typically takes 1-10 mμ sec, and preferably occursduring the so-called horizontal blanking interval of a video image. Eachcolumn is then successively selected for read-out of the voltage storedin the capacitor of that column using column driver 160. The output datafrom CMOS imager 10 is then processed in accordance with the presentinvention as described below.

With reference to the block diagram of FIG. 2, in a preferred embodimentof the present invention, color image processor 202 converts digitizedimager data (output from CMOS imager 10 of FIG. 1) from its nativeformat (such as RGB) into a format more suitable for image compression,such as YCrCb (according to ISO CCIR-601). Once the image data isconverted into appropriate for compression format, the data stream ispassed to highly pipelined compression module 204. In the preferredembodiment of the present invention, compression module 204 implementsJPEG compression at the video rate. In this embodiment, there are anumber of line buffers 206, 208 at the front end of the compressiondesigned to allow two-dimensional processing. In the preferredembodiment of the present invention, JPEG compression module 204implements baseline JPEG compression, as described below in more detailwith reference to FIG. 3. FIFO & Register & CPU Control module 205implements all of the interface control and communicates with each ofthe modules and the outside CPU data bus.

FIG. 3 provides a more detailed block of baseline JPEG compressionmodule 204. The circuitry is arranged in such a way as to pass the datafrom one stage to the next, allowing the entire compression operation tobe performed at the video pixel rate. JPEG compression module 204divides up the image into 8 by 8 pixel blocks in module 300, and thencalculates the fast discrete cosine transform (FDCT) of each block inmodule 301. Quantizer module 302 rounds off the FDCT coefficientsaccording to a specified quantization matrix. This step produces the“lossy” nature of JPEG, but allows for large compression ratios. Zigzagmodule 303 then performs variable length coding on these coefficients,followed by Huffman coding in module 305, which then outputs thecompressed binary bitstream. For decompression, JPEG recovers thequantized DCT coefficients from the compressed data stream, takes theinverse transforms and displays the image.

The present invention utilizes a unique SRAM addressing scheme to reducethe memory area and improve the utilization rate of memory to maximum.Referring back to FIG. 2, the output from Color Image Processing module202 is continually written to the corresponding SRAM 206, 208 line byline. Since JPEG compression module 204 works on 8*8 blocks of data, 8lines of data have to be ready before compression. The challenge is howto read and write to the SRAM at the same time. There are two addressingschemes to address this problem. The first scheme uses a “ping-pong”algorithm, which uses two SRAMs, one to store the data from Color ImageProcessing module, and the other for JPEG compression. This schemeswitches SRAM banks after every interval of 8 lines of data. The secondscheme uses only one SRAM. The JPEG compression module 204 begins toread after 8 lines of data have been written to the SRAM 206, 208. Then,the output from Color Image Processing module 202 is written to thelocation in the SRAM from where the data has just been read. Comparedwith the ping-pong scheme, the latter scheme uses only one-half of theamount of SRAM. In the present invention, the second scheme is utilized,thereby greatly reducing the chip area.

With reference to the block diagram of FIG. 4, the detail of the SRAMaddressing is shown. To reduce the chip area, the SRAM uses the minimumsize to hold 8 lines of image data for JPEG compression. Module 401automatically detects the video size and self-adjusts the addressingscheme. Module 402 delays reading for eight lines so that full 8 linesof data are ready for JPEG processing. Module 404 extracts twodimensional data from the linear SRAM, separates Y, Cb and Cr toreconstruct 8*8 blocks, and outputs the data in block order of Y Y CbCr, while new video data is simultaneously written to the SRAM. In eachblock, the data is output line by line. To provide real time video, thecalculation of read and write addresses is performed “on-the-fly”without overwriting video data. All addresses including Y read address,Cr read address, Cb read address, Y write address, Cr write address, andCb write address are calculated, pixel by pixel, which adds to thecomplexity of the scheme. The following formulas are used for alladdress calculations. The coefficients are adjusted every 8 lines.LineSize denotes the number of columns in the video frame. Address_next=  Clip (Address_current + Delta_current) Delta_next =  Delta_current *( LineSize / 8 ) − ( LineSize − 1 ) * [ Delta_current * ( LineSize / 8)/ ( LineSize−1 ) ] Clip(A) = A − LineSize −1 when A > (LineSize−1) = 2 *( LineSize −1 ) hen A> 2 * ( LineSize −1)

Due to the nature of JPEG encoding, the output data rate of the encoderis variable (intermittent). This might present a problem for the overallsystem architecture, as in the absence of the frame buffer there wouldbe a need to constantly monitor the availability of the compressed datafor transfer to the system memory or direct transmission to the remotesite. This type of system behavior would unnecessarily tie-up systemresources (such as CPU cycles and data bus bandwidth). In order toaddress this problem, the present invention incorporates a relativelysmall memory buffer, FIFO 210, at the output of the encoder. Thisbuffer, being much smaller that a full frame buffer, preserves the costadvantages of the system and allows for periods of fixed-rate dataoutput interspersed with periods of inactivity.

In the preferred embodiment of the present invention, output buffer 210is a dual-ported memory together with pointer control block, allowingthe buffer to function as a FIFO (first-in-first-out). In thisembodiment, the pointer control block allows for storage of the outputof the encoder as soon as it becomes available, while allowingindependent retrieval of the data based on the external requests, aslong as FIFO is not empty. In yet another embodiment of this invention,the FIFO control block generates Half-Full and/or Almost Empty/Over Xbytes flags describing the state of the content of the FIFO. Thesesignals can then be used as an interrupt for external controller,prompting data retrieval cycle and relieving the external controllerfrom the need to constantly monitor data availability in the FIFO.

FIG. 5 shows a more detailed block diagram of the FIFO & Register & CPUControl module, which implements the communication with the othermodules. CPU Interface Control Module 502 communicates with the CPU databus through control signals and bi-directional data bus for variousoperations, such as register read/write, FIFO data read, FIFO currentusage, INT status, etc. Decoder module 503 handles control signaldecoding. Module 506 generates an INT signal according to the currentFIFO status. Reading or writing to a specified register via the RegisterBus (FIG. 2) is coordinated through Register Interface Control module500. FIFO Interface Control module 504 controls the reading process fromFIFO. All interfaces are controlled and synchronized by OverallInterface Control module 501.

In the preferred embodiment of the present invention, the INT signal issupplied to access the internal FIFO over the system data/memory bus. Toread video data correctly from the internal FIFO, the CPU must know thecurrent state of FIFO. The following FIFO conditions will generate theINT signal transition and will also be reflected as the correspondingINT status register bits. The CPU inquiries the INT status register toget the current FIFO states. Based on the FIFO status, the CPU initiatesor stops the video data read process or processes the data.

Bit 0: End of video frame is in FIFO

Bit 1: FIFO overflow

Bit 2: FIFO empty

Bit 3: End of Frame is read from FIFO

Bit 4: X bytes in FIFO where X is programmable

In a preferred embodiment of the present invention, the FIFO outputs areconnected directly to the system data/memory bus, allowing for theaccess to the imager system to be performed over standard systemcommunication channel in a way similar to the memory access. In yetanother embodiment of the invention, the access to the registers/controlfunctions of the imager system itself is also performed through the samebus interface. In this embodiment, the control signals are provided toallow distinguishing between various traffic over the output pins: imageaccess, register write and register read access.

In addition to providing real-time compressed data stream, the imagersystem of the present invention may also need to provide uncompressedvideo stream either in full frame format or in decimated format (such asVGA image decimated to CIF resolution). Accordingly, in anotherembodiment of the present invention, the encoder output (compressed datastream) and the uncompressed video can be multiplexed to the input portof the output memory buffer (FIFO).

A typical processor based system that includes a CMOS imager deviceaccording to the present invention is illustrated generally at 600 inFIG. 6. A processor based system is exemplary of a system having digitalcircuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision system, vehicle navigation system, videotelephone, surveillance system, auto focus system, star tracker system,motion detection system, image stabilization system and data compressionsystem for high-definition television, all of which can utilize thepresent invention.

A processor system, such as a computer system, for example generallycomprises a central processing unit (CPU) 644 that communicates with aninput/output (I/O) device 646 over a bus 652. The CMOS imager 610 alsocommunicates with the system over bus 652. The computer system 600 alsoincludes random access memory (RAM) 648, and, in the case of a computersystem may include peripheral devices such as a floppy disk drive 654and a compact disk (CD) ROM drive 656 which also communicate with CPU644 over the bus 652. As described above, CMOS imager 610 is combinedwith a pipelined JPEG compression module in a single integrated circuit.

The above description and drawings illustrate a preferred embodimentwhich achieves the objects, features and advantages of the presentinvention. It is not intended that the present invention be limited tothe illustrated embodiments. Any modification of the present inventionwhich comes within the spirit and scope of the following claims shouldbe considered part of the present invention.

1-25. (canceled)
 26. A CMOS imaging device integrated on a single chip,comprising: a CMOS image sensor; a color image processing module; animage storage module coupled to said color image processing module; andan image compression module coupled to said image storage module,wherein said image compression module has a pipelined architecture forprocessing image data in a parallel fashion at video rates withoutrequiring a full frame memory buffer, wherein said image compressionmodule implements JPEG compression at video rates, and wherein saidimage storage module comprises a plurality of line buffers at a frontend of the compression module to allow two-dimensional processing.
 27. ACMOS imaging device integrated on a single chip, comprising: a CMOSimage sensor; a color image processing module; an image storage modulecoupled to said color image processing module; and an image compressionmodule coupled to said image storage module, wherein said imagecompression module has a pipelined architecture for processing imagedata in a parallel fashion at video rates without requiring a full framememory buffer, wherein said image compression module implements JPEGcompression at video rates, and wherein said image storage module usesan SRAM addressing scheme to allow maximum utilization rate of memory,comprising reading and writing to one SRAM at the same rate withoutoverwriting.
 28. The CMOS imaging device of claim 27, wherein an addresscalculation formula is used in SRAM addressing.
 29. A CMOS imagingdevice integrated on a single chip, comprising: a CMOS image sensor; acolor image processing module; an image storage module coupled to saidcolor image processing module; an image compression module coupled tosaid image storage module; and a buffer at the output of the imagecompression module to allow for periods of fixed-rate data outputinterspersed with periods of inactivity, wherein said image compressionmodule has a pipelined architecture for processing image data in aparallel fashion at video rates without requiring a full frame memorybuffer, and wherein said image compression module implements JPEGcompression at video rates.
 30. The CMOS imager device of claim 29,wherein the output buffer is a dual-ported memory provided with apointer control block, such that the buffer functions as a FIFO memory.31. The CMOS imager device of claim 30, wherein the pointer controlblock allows for the storage of the output of the encoder as soon as itbecomes available, while allowing independent retrieval of data based onexternal requests.
 32. The CMOS imager device of claim 30, furthercomprising a FIFO & Register & CPU control block to enable registeraccess and FIFO access via a single system data/memory bus.
 33. The CMOSimager device of claim 32, wherein the FIFO & Register & CPU controlblock generates an INT signal reflecting the current state of the FIFO.34. The CMOS imager device of claim 30, wherein the FIFO pointer controlblock generates half-full and almost-empty/full flags reflecting thestate of the content of the FIFO memory.
 35. The CMOS imager device ofclaim 30, wherein the FIFO outputs are connected directly to adata/memory bus of a system, allowing for access to the system to beperformed over standard system communication channels.
 36. The CMOSimager device of claim 35, wherein access to registers and controlfunctions of the imager system is also performed over said data/memorybus.
 37. The CMOS imager device of claim 32, wherein control signals areprovided to distinguish between image access, register write, andregister read traffic over the output pins.
 38. The CMOS imager deviceof claim 30, further comprising circuitry for multiplexing compressedand uncompressed video to an input port of the FIFO memory.
 39. Aprocess for processing image data from a CMOS imager device, comprisingthe steps of: converting an image to image data using a CMOS imagesensor; color image processing said image data from a first format whichis native to a CMOS imager to a second format more suitable for imagecompression; storing said processed image data in a memory; andcompressing said stored image data using a processing module having apipelined architecture for processing image data in a parallel fashionat video rates without requiring a full frame memory buffer, whereinsaid step of compressing the image comprises JPEG compression at videorates, and wherein said step of storing said processed image data in amemory comprises using an SRAM addressing scheme to allow maximumutilization rate of memory, said SRAM addressing scheme comprisingreading and writing to one SRAM at the same rate without overwriting.